1. Field
Various exemplary embodiments of the present invention relate to a semiconductor memory device capable of receiving row and column commands through an independent bus, and performing a dual command addressing operation, and a memory system including the same.
2. Description of the Related Art
FIG. 1 is a timing diagram illustrating an operation of a conventional semiconductor memory device.
The conventional semiconductor memory device cannot receive a row command such as an active or precharge command, and a column command such as a read or write command at the same time, and should receive them in conformity with a predetermined timing condition.
For example, in order to perform a read or write operation, and an active operation for a bank, the conventional semiconductor memory device should receive the read or write command for the bank a time period of tRCD (RAS-CAS Delay) after the active command for the bank. Furthermore, in order to perform a precharge operation, and a read operation for a bank, the conventional semiconductor memory device should receive a precharge command for the bank a time period of tRTP (Read-To-Precharge) after the read command for the bank.
That is, the conventional semiconductor memory device can normally perform the operations only when it receives the row and column commands in conformity with the timing condition such as the tRCD and tRTP, and it cannot perform the operations when it receives the row and column commands at the same time, as illustrated in FIG. 1.